1. Field of the Invention
The present invention relates to an image processing system which has a bus-control function for transferring a large amount of data, such as an image, a character, etc., through a single data bus.
2. Description of the Related Art
Japanese Laid-Open Publication No. 11-120123 discloses a method for controlling a bus in a system where a single common bus is shared by a CPU and function modules which transfer data based on a Direct Memory Access (DMA) transfer method. FIG. 13 is a block diagram showing a bus control system 2000 which uses this bus control method. FIG. 14 is a timing chart showing signals output from the system shown in FIG. 13. The system of FIG. 13 for controlling a bus includes: a bus use permission request minimum time setting register 110 in which a minimum time consumed since a direct memory access controller (DMAC: not shown) or a CPU (not shown) issues a request for a permission to use a bus (hereinafter, referred to as “bus use permission request”) until the bus control system 2000 outputs a bus use permission request is set for each of the direct memory access controller and the CPU: a counter 111 which operates based on a clock of the CPU (CPUCLK); a DMA time setting register 114 for setting a DMA transfer time; and a counter 115 which operates based on a signal indicating the end of a data transfer cycle signal (RDY).
The bus use permission request minimum time setting register 110 outputs to the counter 111 a signal which indicates a set value of the minimum time consumed until a bus use permission is requested. The counter 111 counts the number of cycles of CPUCLK. When the counted number reaches the set value indicated by the signal output from the bus use permission request minimum time setting register 110, the counter 111 outputs a high-level signal to a HOLD request mask 112. The HOLD request mask 112 receives an output signal from the counter 111. When the output signal is at a low level, the HOLD request mask 112 outputs a signal to an AND gate 113 to turn the AND gate 113 off for a predetermined time period after a DMA transfer operation using the bus is completed. Such an arrangement is made for preventing a bus use permission request signal HOLD from being issued after the DMA transfer operation is completed.
In the meantime, the DMA time setting register 114 outputs to the counter 115 a signal which indicates a set value of a DMA transfer time (i.e., “bus cycle value”). The counter 115 counts an RDY signal which indicates the end of a bus cycle. When the counted number reaches the set value indicated by the signal output from the DMA time setting register 114, i.e., when the counted number reaches the bus cycle value, the counter 115 outputs a high-level signal to a reset terminal R of a flip-flop circuit 116. A set terminal S of the flip-flop circuit 116 receives a HOLD ON condition signal. The AND gate 113 logically synthesizes an output signal from the flip-flop circuit 116 with an output signal from the HOLD request mask 112 to output a bus use permission request signal HOLD.
Thus, based on a comparison result of the set values set in the bus use permission request minimum time setting register 110 and the DMA time setting register 114 and respective counted values in the subsequent counters 111 and 115, the bus control system 2000 switches its operation between two different modes: a mode where the system 2000 outputs a HOLD ON condition signal, which is an internal bus request signal, as a bus use permission request signal HOLD from the AND gate 113; and a mode where the bus use permission request signal HOLD is masked by the HOLD request mask 112 for a predetermined time period. Then, each of the CPU and the DMAC changes the set values in the bus use permission request minimum time setting register 110 and the DMA time setting register 114 based on the comparison result of the previous set values set in the bus use permission request minimum time setting register 110 and the DMA time setting register 114. With such an arrangement, as shown in FIG. 14, each of the CPU and the DMACs sets: a DMA transfer time (A), which is a maximum time during which the CPU or DMAC can use the bus for data transfer after the CPU or DMAC obtains a bus use permission; and a bus use permission request minimum time (B), which is a minimum time consumed until a bus use permission can be requested after a DMA transfer operation is completed. By adjusting these times (A) and (B), the bus occupation ratio between the CPU and the DMAC is properly adjusted. In this example, a value corresponding to the bus use permission request minimum time (B) is set in the bus use permission request minimum time setting register 110, and a value corresponding to the DMA transfer time (A) is set in the DMA time setting register 114. In the timing chart shown in FIG. 14, after the DMAC starts transmitting the bus use permission request signal HOLD, and a bus use permission signal HOLDACK is returned to the DMAC, during the DMA transfer time (A), the bus control system 2000 continues to transmit the signal HOLD, thereby continuing to request a permission to use the bus. After the DMA transfer time (A) has elapsed, the request signal is masked by the HOLD request mask 112. Then, after the bus use permission request minimum time (B) has elapsed, the mask is deactivated again, and the bus control system 2000 resumes requesting the permission to use the bus.
The above bus control system 2000 is provided to each of a CPU and DMACs, and set values in registers for each of the CPU and DMACs are adjusted, whereby the bus occupation ratio among the CPU and DMACs is adjusted.
In this bus control method, a mask period during which each of the CPU and DMACs does not issue a bus use permission request is provided. By adjusting the length of this mask period, the frequency at which each of the CPU and DMACs uses a bus (bus occupation ratio) is adjusted. In such a structure, a time period during which neither of the CPU and DMACs cannot use the bus occurs although the bus is unoccupied. Referring to FIG. 14, during the bus use permission request minimum time (B) when a bus use permission request is masked so as not to be output, the other DMACs and/or the CPU connected to the common bus detect the interruption of the bus use permission request. Such a detection operation requires a sufficiently long time, and further, a sufficiently long time period is required after the detection operation is completed until the other DMACs and/or the CPU obtains a permission to use the bus. Furthermore, once the times (A) and (B) have been set, these set times (A) and (B) are effective until a next modification. Thus, even when only one DMAC (or only the CPU) occupy the bus for data transfer, the DMAC (or CPU) cannot use the bus during the bus use permission request minimum time (B).
As described above, the time set in the DMA time setting register 114 (DMA transfer time (A)) is a maximum time during which the CPU or DMAC can continuously occupy the bus for data transfer. However, in some bus arbitration methods, when a bus use permission is requested by a CPU or DMAC having a higher priority, the bus use permission can be handed over to that prior CPU or DMAC. For example, when a CPU or DMAC transfers data to an SDRAM, or the like, i.e., to a device which requires a short overhead time at the beginning of an access but does not require any overhead time for a subsequent access to addresses within the same page, if the bus use permission is handed over from one of the CPU or DMACs to another during the DMA transfer time (A) as described above, the number of accesses (the number of data transfer operations) is increased by the number of times that a hand-over of the bus use permission is made, and accordingly, the total overhead time is increased. As a result, the data transfer efficiency is decreased by the amount of increased total overhead time.
Thus, it is impossible for the above conventional bus control method to achieve a maximum efficiency of the common bus and is therefore not suitable to a system including a function module which performs high-speed image processing based on a DMA transfer method for achieving high-speed image processing.
FIG. 12 is a block diagram showing a high-speed image processing system S3 based on a conventional bus control method. The image processing system S3 includes: a DMAC 100 which transfers data based on a DMA transfer method; a CPU & i/f 102 which transfers a program command and data for system control; function modules 105, 106, and 107 each of which requests a transfer of data; and an arbitration controller 101 for selectively giving a permission to use the bus in response to bus use permission requests from the DMAC 100 and the CPU & i/f 102.
When reading data stored in an external memory 109, such as a CPU program, etc., the CPU & i/f 102 reads the data from the external memory 109 through an external connection terminal for a system bus B1 (terminal B3), an external memory controller 104, and the system bus B1, but not through the bus B2 which is used exclusively for image data (hereinafter, “image data bus B2”). The CPU & i/f 102 transmits a bus use permission request signal CPBREQ to the arbitration controller 101 only when attempting to refer to image data stored in an external memory 108.
The function modules 105, 106, and 107 issue data transfer request signals DREQ-A, DREQ-B, and DREQ-C, respectively, to the DMAC 100. The DMAC 100 receives the data transfer request signals DREQ-A, DREQ-B, and DREQ-C to determine an order of priority for data transfer among the function modules 105, 106, and 107, and transmits a bus use permission request signal DMBREQ to the arbitration controller 101.
In response to the bus use permission request signal DMBREQ from the DMAC 100 and the bus use permission request signal CPBREQ from the CPU & i/f 102, the arbitration controller 101 selectively outputs to the DMAC 100 or the CPU & i/f 102 a signal for permitting to use the image data bus B2, thereby controlling the bus occupation ratio between the DMAC 100 and the CPU & i/f 102. For example, when the DMAC 100 is permitted to use the image data bus B2, image data is transferred to any of the function modules 105, 106, and 107, based on the previously-determined order of priority, through an external connection terminal for the image data bus B2 (terminal B4), an external memory controller 103, and the image data bus B2.
Data processed by the function modules 105, 106, 107, or the CPU & i/f 102 is written in the external memory 108 according to a bus control procedure similar to the above-described procedure.
As described above, in order to achieve a high-speed image processing system based on the conventional bus control method, it is necessary to structure an image processing system S3 including two data buses (the image data bus B2 and the system bus B1) and to connect the two exclusively-used external memories 108 and 109 to the image data bus B2 and the system bus B1, respectively. Thus, when the image processing system S3 is realized based on a large scale integration (LSI) technique, for example, two connection lines are required between the system S3 and the memories 108 and 109. This influences a package size, and furthermore, increases the amount of electric power consumed in an I/O buffer.